This invention relates to a method for producing a semiconductor device with floating gates.
Most non-volatile memories, e.g., EPROMs and EEPROMs, have floating gate MOS transistors used as memory cells. Bit "1" or "0" is stored in each memory cell in accordance with the electrical charge in the floating gate of the MOS transistor. The floating gate is formed on a channel region of a single crystal semiconductor substrate through a first gate insulation layer. A control gate is formed on the floating gate through a second gate insulation layer. The floating gate is charged or discharged in accordarce with the voltage applied on the control gate. For example, when the control gate and drain of the floating gate MOS transistor respectively receive voltages of 20 V and 5 V in the programming mode of the EPROM, hot electrons move from the channel region into the floating gate through the first gate insulation layer. As a result, the floating gate is charged. The electrical charge within the floating gate is preserved since the gate is electrically insulated from the outside by the first and second insulation layers. The floating gate is usually made of polycrystalline silicon.
In the non-volatile memory of this type, the surface region of the substrate is divided by a field insulation layer into a plurality of element areas. The known method of producing this memory will now be explained.
First, a field insulation layer is formed on a semiconductor substrate, thus dividing the surface region of the substrate into element areas. The substrate is subjected to a first oxidation process, forming an oxide layer on the field insulation layer and on the element areas. Then, a first polycrystalline silicon layer is formed on the oxide layer by chemical vapor deposition (CVD). A photoresist pattern is formed on the silicon layer. By using this pattern as a mask, the silicon layer and oxide layer are patterned. More specifically, that portion of the silicon layer which is not covered by the mask is removed from the oxide layer, and the remaining portion is left and used as a floating gate. That portion of the oxide layer which is located directly below the floating gate is left and used as a first gate insulation layer, and the remaining portion is removed from the element area. Thereafter, the entire structure is subjected to the second oxidation, thereby forming an oxide layer on the exposed element area and the floating gate. (Any portion of this oxide layer that covers an element area is to protect the elements which will be formed. Any portion of the oxide layer that covers a floating gate is used as the second gate insulation layer.) Then, a second polycrystalline silicon layer is formed on the oxide layer by vapor-deposition. This second polycrystalline silicon layer is patterned, whereby some portions are removed. The portion left on the oxide layer is used as control gate and connecting line. The control gate is located above the floating gate.
In the method described above, the layer for protecting elements is formed during the second oxidation, together with the second gate insulation layer. Its thickness cannot be controlled independently of that of the second gate insulation layer. Since single crystal silicon is harder to oxidize than polycrystalline silicon, the second gate insulation layer cannot be thinner than the protecting layer.
The protective layer must be thick enough to electrically insulate the semiconductor substrate from the first and second polycrystalline silicon layers. On the other hand, the second gate insulation layer must be thin enough to reduce the energy (i.e. voltage X time) needed for charging and discharging the floating gates. In view of this, the above method, wherein the thicknesses of the protective layer and second gate insulation layer cannot be controlled independently, is disadvantageous.